1. Field
Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a semiconductor device having a 6F2 cell architecture and a method for fabricating the same.
2. Description of the Related Art
With the development of the fabrication technology of semiconductor devices, the size of the semiconductor devices has been reduced, and the integration degree thereof has been rapidly increased. A cell architecture of a memory device, such as DRAM (Dynamic Random Access Memory), changes from 8F2 architecture to 6F2 architecture, for higher integration. Here, F means a minimum critical dimension (CD) applied to the design rule of the memory device.
FIG. 1 is a plan view of a conventional semiconductor device having a 6F2 cell architecture. FIG. 2 is a cross-sectional view taken along a line A-A′ of FIG. 1.
Referring to FIGS. 1 and 2, the conventional semiconductor device having a 6F2 cell architecture includes a plurality of active regions 13 defined by an isolation layer 12 formed in a substrate 11 (e.g., the regions arranged in an oblique direction in FIG. 1), a plurality of buried gates 100 crossing both of the active regions 13 and the isolation layer 12, and a plurality of bit lines 20 extended in a direction perpendicular to the buried gates 100. Each of the buried gates 100 includes a trench 14 formed in the substrate 11, a gate dielectric layer 15 formed on the trench 14, a gate electrode 16 formed on the gate dielectric layer 15 to partially fill the trench 14, and a sealing layer 17 filling the rest of the trench 14. The bit line 20 is coupled to the center portion of the active region 13 by a bit line contact plug 19 passing through an interlayer dielectric layer 18. Although not illustrated in the drawings, storage node contact plugs are coupled to both edges (refer to symbol ‘A’) of the active region 13 which are not covered by the bit line 12.
The conventional semiconductor device has such a structure that the active regions 13 are arranged in an oblique direction at the buried gate 100 and the bit line 20, in order to implement a 6F2 cell architecture. Therefore, there is a limit in securing an exposed area of both edges (refer to symbol ‘A’) of an active region which are to be coupled to storage node contact plugs. Accordingly, it is difficult to secure a sufficient process margin in forming the storage node contact plugs.
Therefore, a method of increasing the CD of the active region 13 in its longitudinal direction, that is, the oblique direction, has been proposed. However, when the longitudinal length of the active region 13 is increased, a bridge may be formed between the active regions 13 positioned on the same oblique line. Furthermore, as the design of the active region 13 is changed, the design of all the components such as the buried gate 100, the bit line contact plug 19, and the bit line 20 which are to be formed by subsequent processes is to be changed. Accordingly, production cost may increase.